Conventional high speed and low power buffer storage systems have evolved over time. FIG. 1 illustrates a first generation buffer storage system 10. There are 2 NFET pass transistors and 2 CFET, which formed a latch. The system 10 uses no pull-up transistors for the latch portion of the cell. The problem with this type of system is that it was slow and unreliable to hold information. FIG. 2 is a second-generation buffer storage system 30. In this system 30 the SRAM cell using high value resistor pull up. The resistor consumes DC current, and is slow when a large array capacity is involved. As the density gets higher, it consumes large DC current and the circuit is slow. FIG. 3 is a third generation buffer storage system 50 which uses thin-film Poly PFET (TFT) as active pull-ups. The TFT is attractive as the PFET and intra circuit connecting stacked in vertical space, hence the cell elements overlaps in the horizontal dimension yielding smallest bulk area. But like its predecessors, it is also slow, and suffers from leakage. FIG. 4 is the latest generation of conventional buffer storage systems 70. The system 70 uses 2 bulk PFET as pull-up in the latch portion of the cell. The problems with this type of system are large cell area, and it is difficult to scale down in operating voltage because of fixed high VT in the CFET.
The more recent configuration uses the topology of 6 transistor cell. All of them are in the Si bulk. The cell size is bulky, but it has been successfully implemented with the latest CFET 0.15 um technology as photolithographic rules for layout.
It is important to realize that the IC cost is closely related to the horizontal cell size as one wishes fit more dice in a wafer. The cell pitches in each cell dimensions are related to the length of the bit lines and word lines hence to the array sizes. The capacitances associated with every main circuit element intra and/or inter cell wise play an important role in speed considerations, and the noise margins are often compromised by the designers with speed in conjunction with the dc/ac power consumptions in the determination of Vcc supply, and signal and acceptable noise levels.
Accordingly, what is needed is a buffer storage system, which overcomes the above-identified problems. The present invention addresses such a need.